.Implementation of area optimization precoder in a 40 Gb/s PolDM-DQPSK system[J].Optoelectronics Letters,2010,6(6):446-448 Implementation of area optimization precoder in a 40 Gb/s PolDM-DQPSK system 周黎明 Key Laboratory of Information Photonics and Optical Communications,Beijing University of Posts and Telecommunications,Ministry of Education； Abstract:       In this paper, a new model based on an improved Brent Kung (BK) parallel prefix network (PPN) algorithm is proposed and realized in the field programmable gate array (FPGA). This model is employed in the implementation of 20 Gb/s differential quadrature phase-shift keying (DQPSK) precoder in 40 Gb/s polarization division multiplex (PolDM) DQPSK system. In the computation process, the computation complexity (area) optimization with fan-out limited is achieved. In the implementation, 770 FPGA slice registers are utilized, which save about 60% logic resources compared with the previous Kogge Stone (KS) algorithm. Hits: 4071 Download times: 267 View Full Text    Download reader