| Kang-ping Zhong,Tang-jun Li,Nan Jia,Jian Sun,Mu-guang Wang.An improved multiplier-free feed-forward carrier phase estimation for dual-polarization QPSK modulation format[J].Optoelectronics Letters,2013,9(4):305-308 |
| An improved multiplier-free feed-forward carrier phase estimation for dual-polarization QPSK modulation format |
| Author Name | Affiliation | E-mail | | Kang-ping Zhong | State Key Laboratory of All Optical Network & Advanced Telecommunication Network, Beijing Jiaotong University, Beijing, 100044, China
Institute of Lightwave Technology, Beijing Jiaotong University, Beijing, 100044, China | 09111023@bjtu.edu.cn | | Tang-jun Li | State Key Laboratory of All Optical Network & Advanced Telecommunication Network, Beijing Jiaotong University, Beijing, 100044, China
Institute of Lightwave Technology, Beijing Jiaotong University, Beijing, 100044, China | | | Nan Jia | State Key Laboratory of All Optical Network & Advanced Telecommunication Network, Beijing Jiaotong University, Beijing, 100044, China
Institute of Lightwave Technology, Beijing Jiaotong University, Beijing, 100044, China | | | Jian Sun | State Key Laboratory of All Optical Network & Advanced Telecommunication Network, Beijing Jiaotong University, Beijing, 100044, China
Institute of Lightwave Technology, Beijing Jiaotong University, Beijing, 100044, China | | | Mu-guang Wang | State Key Laboratory of All Optical Network & Advanced Telecommunication Network, Beijing Jiaotong University, Beijing, 100044, China
Institute of Lightwave Technology, Beijing Jiaotong University, Beijing, 100044, China | |
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| Abstract: |
| An improved multiplier-free feed-forward carrier phase estimation algorithm is proposed for dual-polarization quadrature-phase-shift-keying (DP-QPSK) with coherent detection. The bit error rate (BER) performance, block length effect and linewidth tolerance of the proposed algorithm are evaluated for a 112 Gbit/s DP-QPSK system. A linewidth symbol duration product of 2.9×10?4 is demonstrated for 1 dB optical signal-to-noise-ratio (OSNR) penalty at BER of 10?3 for the proposed algorithm. The hardware complexity of the proposed multiplier-free algorithm is demonstrated to be much lower than that of the 4th power algorithm. |
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